Recent research works on array and pipeline processors are also summarized. The chapter concludes with the evaluation of the performance of pipeline and array processors and explores various optimization techniques for vector operations.
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- A learnable parallel processing architecture towards unity of memory and computing?
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- A learnable parallel processing architecture towards unity of memory and computing;
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Amazon Drive Cloud storage from Amazon. Alexa Actionable Analytics for the Web. The first of these works proposes a directory-based conflict detection scheme, which can alleviate the performance degradation that eager systems experience when contention is high, and it has the potential to minimize the effect of false positives when hash signatures are used for transactional book-keeping.
This work was published in the HiPC conference [Titos]. Later, we proposed a scheme for speculative resolution of conflicts that allows a writer transactions to continue its execution past conflicting access with other concurrent readers.
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Furthermore, we have designed a hybrid HTM system that is capable of selecting the most appropriate policy, eager or lazy, for managing each individual cache line, depending on the past behaviour of the line in regards to contention. This data-centric design combines the best of both worlds, as it is able to achieve truely parallel commits when contention is low, while being able to extract good concurrency in situations of high contention.
This proposal was published in ICS [Titosa]. Furthermore, we have thoroughly analised the implications that common structural optimizations such as store buffering have in the performance of both eager and lazy systems, which had been ignored in the literature. Our findings confirm that when write buffering is employed, the behaviour of eager systems is lazified and both HTM designs exhibit comparable performance, debunking the generalized perception that lazy systems consistently outperform their eager counterparts.
In the context of consolidated servers, we proposed a operating system based distance-aware round-robing mapping policy that tries to map memory pages to the cache bank belonging to the core that most frequently accesses the blocks within that page which was presented in HiPC [Ros].
Architecture of a massively parallel processor
Recently, we analized previously proposed cache-coherence protocols for server consolidation using virtualization, found problems with the handling of shared memory i. The full list of publications can be found visiting the personal web pages of the group members, where you could download most of the papers in pdf format.
Current technology trends are increasing the number of available transistors per chip. Nonetheless, these trends are also making these transistors more prone to permanent, intermittent and transient faults. To overcome these problems, we need to develop new architectural techniques that will ensure the reliability of the chip. Traditionally, this can be achieved by adding a significant amount of redundant hardware, something which increases the cost of the device and decreases its performance and energy efficiency.
Vector Computer Architecture and Processing Techniques - ScienceDirect
Our main goal consists of providing fault-tolerance with minimal performance degradation. For achieving this, we propose fault-tolerance techniques both at the microarchitectural level and at the interconnection network level. With this proposal, we achieve an improvement in terms of both performance degradation and area overhead compared to previous works.
We leverage the already introduced hardware of LogTM-SE to provide a consistent view of the memory between master and slave threads through a virtualized memory log, achieving both transient fault detection and recovery, more scalability, higher decoupling and lower performance overhead than previous proposals. For handling faults that happen in the on-chip interconnection network of CMPs, we propose to add fault-tolerance at the level of the cache coherence protocol instead of at the level of the interconnection network itself.
We have shown the viability of our approach and we have developed several fault-tolerant cache coherence protocols.